Atari 2600 Specifications |
Technical Data |
CPU: 6507, 8bit, 1.19MHz (cutdown 6502 with only 8K address space) RAM: 128 Bytes (additional 128 or 256 bytes in some cartridges) VRAM: None (Picture controlled by I/O Ports only) ROM: External Game Cartridge (usually 2KB or 4KB, or banked 2x4KB) |
Output: Line-by-line (Registers must be updated each scanline) Resolution: 160x192 pixels (NTSC 60Hz), 160x228 pixels (PAL 50Hz) Playfield: 40 dots horizontal resolution (rows of 4 pixels per dot) Colors: 4 colors at once (one color per object) Palette: 128 colors (NTSC), 104 colors (PAL), 8 colors (SECAM) Sprites: 2 sprites of 8pix width, 3 sprites of 1pix width |
I/O: Two 8bit I/O ports, six 1bit Input ports Timer: One 8bit Timer (with prescaler; 1,8,64,1024 machine cycles) Audio: Two sound channels (with Frequency, Volume, Noise control) |
Switches: Color/Mono Switch (PAL/NTSC only), and two Difficulty Switches Buttons: Select Button, Reset Button (or Switches in older consoles) Hardware: Power Switch, TV Channel Select Switch (not software controlled) |
Slot: One 24 pin Cartridge Slot (with 4K address bus) Controls: Two 9 pin Joystick ports (also used for Paddles, Keyboards) TV: One Cinch Socket (Video/Audio TV Signal) Power: 9V DC, 500mA (internally converted to 5V DC) |
Memory and I/O Map |
0000-002C TIA Write 0000-000D TIA Read (sometimes mirrored at 0030-003D) 0080-00FF PIA RAM (128 bytes) 0280-0297 PIA Ports and Timer F000-FFFF Cartridge Memory (4 Kbytes area) |
00 VSYNC ......1. vertical sync set-clear 01 VBLANK 11....1. vertical blank set-clear 02 WSYNC <strobe> wait for leading edge of horizontal blank 03 RSYNC <strobe> reset horizontal sync counter 04 NUSIZ0 ..111111 number-size player-missile 0 05 NUSIZ1 ..111111 number-size player-missile 1 06 COLUP0 1111111. color-lum player 0 and missile 0 07 COLUP1 1111111. color-lum player 1 and missile 1 08 COLUPF 1111111. color-lum playfield and ball 09 COLUBK 1111111. color-lum background 0A CTRLPF ..11.111 control playfield ball size & collisions 0B REFP0 ....1... reflect player 0 0C REFP1 ....1... reflect player 1 0D PF0 1111.... playfield register byte 0 0E PF1 11111111 playfield register byte 1 0F PF2 11111111 playfield register byte 2 10 RESP0 <strobe> reset player 0 11 RESP1 <strobe> reset player 1 12 RESM0 <strobe> reset missile 0 13 RESM1 <strobe> reset missile 1 14 RESBL <strobe> reset ball 15 AUDC0 ....1111 audio control 0 16 AUDC1 ....1111 audio control 1 17 AUDF0 ...11111 audio frequency 0 18 AUDF1 ...11111 audio frequency 1 19 AUDV0 ....1111 audio volume 0 1A AUDV1 ....1111 audio volume 1 1B GRP0 11111111 graphics player 0 1C GRP1 11111111 graphics player 1 1D ENAM0 ......1. graphics (enable) missile 0 1E ENAM1 ......1. graphics (enable) missile 1 1F ENABL ......1. graphics (enable) ball 20 HMP0 1111.... horizontal motion player 0 21 HMP1 1111.... horizontal motion player 1 22 HMM0 1111.... horizontal motion missile 0 23 HMM1 1111.... horizontal motion missile 1 24 HMBL 1111.... horizontal motion ball 25 VDELP0 .......1 vertical delay player 0 26 VDELP1 .......1 vertical delay player 1 27 VDELBL .......1 vertical delay ball 28 RESMP0 ......1. reset missile 0 to player 0 29 RESMP1 ......1. reset missile 1 to player 1 2A HMOVE <strobe> apply horizontal motion 2B HMCLR <strobe> clear horizontal motion registers 2C CXCLR <strobe> clear collision latches |
30 CXM0P 11...... read collision M0-P1, M0-P0 (Bit 7,6) 31 CXM1P 11...... read collision M1-P0, M1-P1 32 CXP0FB 11...... read collision P0-PF, P0-BL 33 CXP1FB 11...... read collision P1-PF, P1-BL 34 CXM0FB 11...... read collision M0-PF, M0-BL 35 CXM1FB 11...... read collision M1-PF, M1-BL 36 CXBLPF 1....... read collision BL-PF, unused 37 CXPPMM 11...... read collision P0-P1, M0-M1 38 INPT0 1....... read pot port 39 INPT1 1....... read pot port 3A INPT2 1....... read pot port 3B INPT3 1....... read pot port 3C INPT4 1....... read input 3D INPT5 1....... read input |
80..FF RAM 11111111 128 bytes RAM (in PIA chip) for variables and stack 0280 SWCHA 11111111 Port A; input or output (read or write) 0281 SWACNT 11111111 Port A DDR, 0= input, 1=output 0282 SWCHB 11111111 Port B; console switches (read only) 0283 SWBCNT 11111111 Port B DDR (hardwired as input) 0284 INTIM 11111111 Timer output (read only) 0285 INSTAT 11...... Timer Status (read only, undocumented) 0294 TIM1T 11111111 set 1 clock interval (838 nsec/interval) 0295 TIM8T 11111111 set 8 clock interval (6.7 usec/interval) 0296 TIM64T 11111111 set 64 clock interval (53.6 usec/interval) 0297 T1024T 11111111 set 1024 clock interval (858.2 usec/interval) |
F000-FFFF ROM 11111111 Cartridge ROM (4 Kbytes max) F000-F07F RAMW 11111111 Cartridge RAM Write (optional 128 bytes) F000-F0FF RAMW 11111111 Cartridge RAM Write (optional 256 bytes) F080-F0FF RAMR 11111111 Cartridge RAM Read (optional 128 bytes) F100-F1FF RAMR 11111111 Cartridge RAM Read (optional 256 bytes) 003F BANK ......11 Cart Bank Switching (for some 8K ROMs, 4x2K) FFF4-FFFB BANK <strobe> Cart Bank Switching (for ROMs greater 4K) FFFC-FFFD ENTRY 11111111 Cart Entrypoint (16bit pointer) FFFE-FFFF BREAK 11111111 Cart Breakpoint (16bit pointer) |
Memory Mirrors |
Video |
Video Synchronization and Blanking |
Bit Expl. 0 Not used 1 Vertical Sync (0=Stop sync, 1=Start sync) 2-7 Not used |
Bit Expl. 0 Not used 1 Vertical Blank (0=Stop blanking, 1=Start blanking) 2-5 Not used 6 INPT4-INPT5 Control (0=Normal Input, 1=Latched Input) 7 INPT0-INPT3 Control (0=Normal Input, 1=Dumped to ground) |
Video Dimensions and Timings |
Type_______NTSC__PAL/SECAM______ V-Sync 3 3 scanlines V-Blank 37 45 scanlines (upper border) Picture 192 228 scanlines Overscan 30 36 scanlines (lower border) Frame Rate 60 50 Hz Frame Time 262 312 scanlines |
Blanking 22.6 machine clocks (68 color clocks) Picture 53.3 machine clocks (160 color clocks) (160 pixels) Total 76.0 machine clocks (228 color clocks) |
Video Color Clock: 3.579545 MHz (NTSC), 3.546894 MHz (PAL) CPU Machine Clock: 1.193182 MHz (NTSC), 1.182298 MHz (PAL) |
Video Playfield |
Normal (REF=0) : PF0.4-7 PF1.7-0 PF2.0-7 PF0.4-7 PF1.7-0 PF2.0-7 Mirror (REF=1) : PF0.4-7 PF1.7-0 PF2.0-7 PF2.7-0 PF1.0-7 PF0.7-4 |
Bit Expl. 0 Playfield Reflection (0=Normal, 1=Mirror right half) 1 Playfield Color (0=Normal, 1=Score Mode, only if Bit2=0) 2 Playfield/Ball Priority (0=Normal, 1=Above Players/Missiles) 3 Not used 4-5 Ball size (0..3 = 1,2,4,8 pixels width) 6-7 Not used |
Video MOB Shape/Enable |
Bit Expl. 0-2 Player-Missile number & Player size (See table below) 3 Not used ??? 4-5 Missile Size (0..3 = 1,2,4,8 pixels width) 6-7 Not used |
0 One copy (X.........) 1 Two copies - close (X.X.......) 2 Two copies - medium (X...X.....) 3 Three copies - close (X.X.X.....) 4 Two copies - wide (X.......X.) 5 Double sized player (XX........) 6 Three copies - medium (X...X...X.) 7 Quad sized player (XXXX......) |
Bit Expl. 0-7 Eight dots player shape (0=Transparent, 1=Player color) |
Bit Expl. 0 Not used 1 Missile/Ball Enable (0=Transparent, 1=Missile/Ball color) 2-7 Not used |
Bit Expl. 0-2 Not used 3 Reflect Player Graphics (0=Normal/MSB first, 1=Mirror/LSB first) 4-7 Not used |
Bit Expl. 0 Vertical Delay (0=No delay, 1=Delay until writing to GRP0/GRP1) 1-7 Not used |
Video MOB Horizontal Positioning |
Bit Expl. 0 Not used 1 Reset Missile to Player (0=Normal, 1=Hide and Lock on player) 2-7 Not used |
Video MOB Horizontal Motion |
Bit Expl. 0-3 Not used 4-7 Signed Motion Value (-8..-1=Right, 0=No motion, +1..+7=Left) |
NewPos = ( OldPos +/- Motion ) MOD 160 |
6,4,4,2,0 ;-more before blanking, disp RIGHT \ -2,-2,-4,-6,-8,-8 ;-area before blanking, disp LEFT / 14 dup (0) ;-blanking area, disp ZERO | 2,2,4,6,8,8,10,12 ;-area after blanking, disp RIGHT \ 8,8,8,8,8... ;-remaining area, disp FAST RIGHT ""--__ |
-1,-2,-2,-3,-4,-5,-5,-6,-7,-8,-8 ;disp LEFT / 14 dup (0) ;-blanking area, disp ZERO | 1,1,2,3,4,4,5,6 ;-area after blanking, disp RIGHT \ 0,0,0,0,0... ;-remaining area, disp ZERO | |
Video Collision |
Bit Expl. 0-5 Not used 6,7 Two Collsion Flags (0=No collision, 1=Collision occured) |
Video Colors |
Bit Expl. 0 Not used 1-3 NTSC/PAL Luminance (0-7) - SECAM: RGB (0-7) - Mono TV: Grayshade (0-7) 4-7 NTSC/PAL Color (0-15) - SECAM: Ignored - Mono TV: Ignored |
NTSC Colors PAL Colors NTSC/PAL Lum. SECAM RGB 0 White 0 White 0 Black 0 Black 1 Gold 1 Same as color 0 1 Dark grey 1 Blue 2 Orange 2 Yellow 2 ... 2 Red 3 Bright orange 3 Green-yellow 3 Grey 3 Magenta 4 Pink 4 Orange 4 ... 4 Green 5 Purple 5 Green 5 ... 5 Cyan 6 Purple-blue 6 Pink-orange 6 Light grey 6 Yellow 7 Blue 7 Green-blue 7 White 7 White 8 Blue 8 Pink 9 Light blue 9 Turquois A Torq. A Pink-blue B Green-blue B Light blue C Green C Blue-red D Yellow-green D Dark blue E Orange-green E Same as color 0 F Light orange F Same as color 0 |
Video Priority |
Priority Color Objects 1 (highest) COLUP0 P0, M0 (and left side of PF in SCORE-mode) 2 COLUP1 P1, M1 (and right side of PF in SCORE-mode) 3 COLUPF BL, PF (only BL in SCORE-mode) 4 (lowest) COLUBK BK |
Priority Color Objects 1 (highest) COLUPF PF, BL (always, the SCORE-bit is ignored) 2 COLUP0 P0, M0 3 COLUP1 P1, M1 4 (lowest) COLUBK BK |
Interval Timer |
Bit Expl. 0-5 Not used (Seems to be always zero) 6 Underflow Flag 1 (1=Underflow, since last INSTAT read) 7 Underflow Flag 2 (1=Underflow, since last TIMnnT write) |
Audio |
Bit 0-3, Volume 0-15 (0=Off, 15=Loudest) |
Bit 0-4, Frequency Divider (0..31 = 30KHz/1..30KHz/32) |
PAL: 31113.1 Hz (3.546894MHz/114) NTSC: 31399.5 Hz (3.579545MHz/114) |
These registers control nine bit shift counters, and may select different shift counter feedback taps and count lengths to produce a variety of noise and tone qualities. |
0 set to 1 8 9 bit poly (white noise) 1 4 bit poly 9 5 bit poly 2 div 15 -> 4 bit poly A div 31 : pure tone 3 5 bit poly -> 4 bit poly B set last 4 bits to 1 4 div 2 : pure tone C div 6 : pure tone 5 div 2 : pure tone D div 6 : pure tone 6 div 31 : pure tone E div 93 : pure tone 7 5 bit poly -> div 2 F 5 bit poly div 6 |
x Rep Pattern Shape 0 1 ---------------------------------------------------------------------- 1 15 ----___-__--_-_----___-__--_-_----___-__--_-_----___-__--_-_----___-__ 2 465 --------------------------------------------------------------________ 3 465 ------______-___---__-----___-------___----___--__--_____---------___- 4 2 -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_ 5 2 -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_ 6 31 ------------------_____________------------------_____________-------- 7 31 -----___--_---_-_-____-__-_--__-----___--_---_-_-____-__-_--__-----___ 8 511 ---------_____----_-----___-_---__--__-_____-__-_-__---_--_-___----__- 9 31 -----___--_---_-_-____-__-_--__-----___--_---_-_-____-__-_--__-----___ A 31 ------------------_____________------------------_____________-------- B 1 ---------------------------------------------------------------------- C 6 ---___---___---___---___---___---___---___---___---___---___---___---_ D 6 ---___---___---___---___---___---___---___---___---___---___---___---_ E 93 -------------------------------------------------_____________________ F 93 ----------_____---_______----__________------___------____---------___ |
poly old bits output new bits calculation 4bit abcd d zabc z = c xor d 5bit abcde e zabcd z = c xor e 9bit abcdefghi i zabcdefgh z = e xor i |
4bit 5bit 9bit poly 5bit->4bit ---xx- ---x-x- -----x---x- ---x-x---xx- 1111 11111 111111111 10011 1111 0111 01111 011111111 11001 0111 0011 00111 001111111 11100 ...1 0001 00011 000111111 11110 ...1 1000 10001 000011111 11111 0011 0100 11000 000001111 01111 0001 0010 01100 100000111 00111 1000 1001 10110 110000011 00011 0100 1100 11011 111000001 10001 0010 0110 11101 111100000 11000 ...0 1011 01110 011110000 01100 ...0 0101 10111 101111000 10110 ...0 1010 01011 110111100 11011 1001 1101 10101 111011110 11101 1100 1110 01010 111101111 01110 ...0 1111 00101 111110111 10111 0110 0111 00010 011111011 01011 1011 0011 00001 001111101 10101 0101 0001 10000 000111110 01010 ...1 1000 01000 100011111 00101 1010 0100 00100 010001111 00010 ...0 0010 10010 101000111 00001 1101 1001 01001 110100011 10000 ...1 1100 10100 111010001 01000 ...1 0110 11010 011101000 00100 ...1 1011 01101 001110100 10010 ...1 0101 00110 100111010 01001 1110 1010 10011 110011101 10100 ...0 1101 11001 011001110 11010 ...0 1110 11100 001100111 01101 1111 1111 11110 100110011 00110 ...1 |
Controllers |
Controllers: Joysticks |
Pin PlayerP0 PlayerP1 Expl. 1 SWCHA.4 SWCHA.0 Up (0=Moved, 1=Not moved) 2 SWCHA.5 SWCHA.1 Down ("") 3 SWCHA.6 SWCHA.2 Left ("") 4 SWCHA.7 SWCHA.3 Right ("") 6 INPT4.7 INPT5.7 Button (0=Pressed, 1=Not pressed) |
Pin Bit Expl. 5,9 VBLANK.7 INPT0-INPT3 Control (0=Normal Input, 1=Dumped to ground) |
Pin PlayerP0 PlayerP1 Expl. 5 INPT0.7 INPT2.7 2nd Button (1=Pressed/Charged) 9 INPT1.7 INPT3.7 3rd Button (1=Pressed/Charged) |
Controllers: Paddles |
Pin Bit Expl. 3 SWCHA.2 Paddle #3 button (right paddle, P1) (0=Pressed) 4 SWCHA.3 Paddle #2 button (left paddle, P1) 3 SWCHA.6 Paddle #1 button (right paddle, P0) 4 SWCHA.7 Paddle #0 button (left paddle, P0) |
Pin Bit Expl. 5,9 VBLANK.7 INPT0-INPT3 Control (0=Normal Input, 1=Dumped to ground) |
Pin Bit Expl. 9 INPT3.7 Paddle #3 pot (right paddle, P1) (1=Charged/Ready) 5 INPT2.7 Paddle #2 pot (left paddle, P1) 9 INPT1.7 Paddle #1 pot (right paddle, P0) 5 INPT0.7 Paddle #0 pot (left paddle, P0) |
Position Left <--------- Center ---------> Right Degrees -135 -90 -45 0 +45 +90 +135 Ohms 1M ... ... 500K ... ... 0 Scanlines 380 ... ... 190 ... ... 0 |
Controllers: Keypad |
Pin PlayerP0 PlayerP1 Dir Expl. Keys 1 SWCHA.4 SWCHA.0 Out Upper row (0=Select) 1,2,3 2 SWCHA.5 SWCHA.1 Out Second row (0=Select) 4,5,6 3 SWCHA.6 SWCHA.2 Out Third row (0=Select) 7,8,9 4 SWCHA.7 SWCHA.3 Out Bottom row (0=Select) *,0,# 5 INPT0.7 INPT2.7 In Left column (0=Pressed) 1,4,7,* 9 INPT1.7 INPT3.7 In Middle column (0=Pressed) 2,5,8,0 6 INPT4.7 INPT5.7 In Right column (0=Pressed) 3,6,9,# |
Controllers: Steering |
Indy 500 and Stell-A-Sketch (homebrew program) |
Pin PlayerP0 PlayerP1 Expl. 1 SWCHA.4 SWCHA.0 Pos (0=Closed, 1=Not closed) 2 SWCHA.5 SWCHA.1 Pos ("") 6 INPT4.7 INPT5.7 Button (0=Pressed, 1=Not pressed) |
________ | BIT1 |____________________ Pin 1 (Up) | BIT2 |__ |__ ____ | BIT3 |__ |XOR \___ Pin 2 (Down) | BIT0 |___________|____/ | Rotary | |__ ____ Pin 7 (Vcc) | DIP | [10K] | Switch |____________________ Pin 8 (Gnd) | GND | | Button |________| |___o--o____ Pin 6 (Button) |
Controllers: Lightgun |
Sentinel (1990) (Atari) Shooting Arcade (prototype only) Bobby needs Food (homebrew) Guntest (homebrew test program) (Eckhard Stolberg) |
1 trigger (active high) 2 - 3 - 4 - 5 - 6 light sensor (active low) 7 +5V 8 GND 9 - |
bit 4 of SWCHA = 1 if the trigger is pressed, 0 otherwise. bit 7 of INPT4 = 0 if the sensor sees light, 1 otherwise. |
bit 0 of SWCHA = 1 if the trigger is pressed, 0 otherwise. bit 7 of INPT5 = 0 if the sensor sees light, 1 otherwise. |
Controllers: Trackball |
GND--||-------o----------------------------------- XCLK/Pin2 ;\Trackball 470pF | .------------. 100nF (YCLK/Pin4) ;/Mode VCC---[10K]---o VCC--|RST 4538 C|--||--. | VCC--|-TR multi RC|------o--[91K]--VCC X1--o--[430K]---o .--|+TR vibr. Q|--. (Y1) | .-----. | | '------------' | .----. '--|+ | | | .--------. o--|4011| |LM339|--o-----o--|D | | |NAND|-- Right/Pin4 ;\ Vref--|- | | Q|---------| | (Down/Pin2) ; '-----' | 4113 /Q|---. | '----' ; Joystick VCC---[10K]---. | flip | | | .----. ; Mode | | flop | | '--|4011| ; X2--o--[430K]---o | | | |NAND|-- Left/Pin2 ; (Y2) | .-----. | GND--|SET | o-----| | (Up/Pin1) ;/ '--|+ | | GND--|RES | | '----' |LM339|--o--------|CK | '------------- XDIR/Pin1 ;\Trackball Vref--|- | '--------' (YDIR/Pin3) ;/Mode '-----' ____ Vref--------. GND--o o--. VCC--[L1]--Pin7 ;\Supply | ____ | GND--------Pin8 ; and Fire GND--[8K1]--o--[100K]---VCC GND--o o--o-------- Fire/Pin6 ;/ |
LM339 quad comperator/amplifier ;-mouse and all trak-ball versions 4113 dual flip flop ;\ 4538 dual multivibrator ; all trak-ball versions only 4011 quad NAND gates ;/ 4019 eight-to-four multiplexer ;-trak-ball with trackball-mode only 4030 quad XOR gates ;-trak-ball with mouse-mode only SW two position switch ;-trak-ball with trackball or mouse mode only |
Type/Modes Joystick Trackball Atari-Mouse Amiga-Mouse Old Atari CX-22 Trak-Ball Yes - - - New Atari CX-22 Trak-Ball Yes Yes - - Old Atari CX-80 Trak-Ball Yes Yes - - New Atari CX-80 Trak-Ball Yes? - Yes - Atari Mouse - - Yes - Amiga Mouse - - - Yes |
Controllers: Other |
Video Jogger (Exus) Video Reflex (Exus) |
Mogul Maniac (Amiga) Off Your Rocker (Amiga) Surf's Up (Amiga) |
Controllers: Console Switches |
Bit Expl. SWCHB.0 Reset Button (0=Pressed) SWCHB.1 Select Button (0=Pressed) SWCHB.2 Not used SWCHB.3 Color Switch (0=B/W, 1=Color) (Always 0 for SECAM) SWCHB.4-5 Not used SWCHB.6 P0 Difficulty Switch (0=Beginner (B), 1=Advanced (A)) SWCHB.7 P1 Difficulty Switch (0=Beginner (B), 1=Advanced (A)) |
Controllers: I/O Registers |
Bit Expl. 0-7 Data Inputs or Outputs (Direction depends on SWACNT) |
Bit Expl. 0-7 Data Direction for SWCHA Bit 0-7 (0=Input, 1=Output) |
Bit Expl. 0-7 Data Inputs or Outputs (Direction depends on SWBCNT) |
Bit Expl. 0-7 Data Direction for SWCHB Bit 0-7 (0=Input, 1=Output) |
Controllers: External Port Pin-Outs |
Pin Port 1 Port 2 Joystick Paddles Keyboard .---------. 1 SWCHA.4 SWACH.0 Up - Row 0 | 1 2 3 4 5 | 2 SWCHA.5 SWACH.1 Down - Row 1 \ 6 7 8 9 / 3 SWCHA.6 SWCHA.2 Left Button 1 Row 2 '-------' 4 SWCHA.7 SWCHA.3 Right Button 0 Row 3 5 INPT0 INPT2 - Pot 0 Column 0 6 INPT4 INPT5 Button - Column 2 7 +5V +5V - VCC/Pot Pull-ups 8 GND GND GND GND/Butt - 9 INPT1 INPT3 - Pot 1 Column 1 |
Cartridges |
Cart Raw ROM (unbanked) |
Cart 4K-Banking (by Port FFxxh) |
Size Banks FFF4 FFF5 FFF6 FFF7 FFF8 FFF9 FFFA FFFB 2K,4K 1 - - - - - - - - 8K 2 - - - - 0 1 - - 12K 3 - - - - 0 1 2 - 16K 4 - - 0 1 2 3 - - 32K 8 0 1 2 3 4 5 6 7 |
Cart 2K-Banking (by Port FFxxh) |
FFE0-FFE7 bank 0-7 for F000-F7FF FFE8 used by burgtime ONLY, don't know, initialize something ??? expansion RAM at F800-F9FF bank 7 fixed at FA00-FFFF |
Cart 1K-Banking (by Port FFxxh) |
FFE0-FFE7 bank 0-7 for F000-F3FF FFE8-FFEF bank 0-7 for F400-F7FF FFF0-FFF7 bank 0-7 for F800-FBFF bank 7 fixed at FC00-FFFF |
Cart 2K-Banking (by Port 3Fh) |
MOV [3F],n bank 0-2 for F000-F7FF bank 3 fixed at F800-FFFF |
Cart 4K-Banking (by JSR/RTS opcodes) |
bank1 select by CALL DXXX opcode, bank0 select by RET FXXX opcode |
Cart Pitfall 2 |
Channel Data Mask Max/y1 Min/y2 Lsb Msb ch0 video 1008 1010 1040 1048 1050 1058 ch1 video 1009 - - - 1051 1059 ch2 video 100A - - - 1052 105A ch3 video 100B 1013 1043 104B 1053 105B ch4 video 100C - - - 1054 105C ch5 audio /--\ - 1045 104D 1055 105D ch6 audio 1006 - 1046 104E 1056 105E ch7 audio \--/ - 1047 104F 1057 105F poly8 1000 - - - - - bank 0 1FF8 - - - - - bank 1 1FF9 - - - - - |
Cart Expansion RAM |
Cart Type 4K-Banking 4K-Banking 2K-Banking RAM Size 128 bytes 256 bytes 256 bytes RAM Write Area F000-F07F F000-F0FF F800-F8FF RAM Read Area F080-F0FF F100-F1FF F900-F9FF ROM Size 3.75K 3.5K 1.5K ROM Area F100-FFFF F200-FFFF FA00-FFFF |
Cart Pin-Outs |
+--------------------------------------------------+ | | | /EX +5V A8 A9 A11 A10 A12 D7 D6 D5 D4 D3 | | A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND | +--------------------------------------------------+ |
Cart Summary and General Info |
ROM Type:Port RAM Used by how many games 1K - - 1 (Cave1k - when removing 2K-padding) 2K - - 51 4K - - 296 8K 2x4K - 111 8K 2x4K 128 3 (Stargate,Defendr2,Elevator) 8K 2x4K:JSR - 1 (Decathln) 8K 4x2K:3Fh - 6 (Springer,Espial,Minrvol2,Mnr2049r,Riverp,Polaris) 8K 4x2K 256 1 (Bnj - when removing 16K padding) 8K 8x1K - 13 10K 2x4K+2K - 1 (Pitfall2, with sequential data channels) 12K 3x4K 256 3 (Mtnking,Omegarac,Tunlrunr) 16K 4x4K - 31 16K 4x4K 128 13 16K 8x2K - 2 (Burgtime,He_man) 32K 8x4K 128 1 (Fatalrun) |
FFFC-FFFD CPU Entrypoint (16bit pointer) FFFE-FFFF CPU Breakpoint (16bit pointer) |
CPU 65XX Microprocessor |
CPU Registers and Flags |
Bits Name Expl. 8 A Accumulator 8 X Index Register X 8 Y Index Register Y 16 PC Program Counter 8 S Stack Pointer (see below) 8 P Processor Status Register (see below) |
Bit Name Expl. 0 C Carry (0=No Carry, 1=Carry) 1 Z Zero (0=Nonzero, 1=Zero) 2 I IRQ Disable (0=IRQ Enable, 1=IRQ Disable) 3 D Decimal Mode (0=Normal, 1=BCD Mode for ADC/SBC opcodes) 4 B Break Flag (0=IRQ/NMI, 1=RESET or BRK/PHP opcode) 5 - Not used (Always 1) 6 V Overflow (0=No Overflow, 1=Overflow) 7 N Negative/Sign (0=Positive, 1=Negative) |
CPU Memory Addressing |
Name Native Nocash Implied - A,X,Y,S,P Immediate #nn nn Zero Page nn [nn] Zero Page,X nn,X [nn+X] Zero Page,Y nn,Y [nn+Y] Absolute nnnn [nnnn] Absolute,X nnnn,X [nnnn+X] Absolute,Y nnnn,Y [nnnn+Y] (Indirect,X) (nn,X) [[nn+X]] (Indirect),Y (nn),Y [[nn]+Y] |
CPU Memory and Register Transfers |
Opcode Flags Clk Native Nocash Expl. A8 nz---- 2 TAY MOV Y,A ;Y=A AA nz---- 2 TAX MOV X,A ;X=A BA nz---- 2 TSX MOV X,S ;X=S 98 nz---- 2 TYA MOV A,Y ;A=Y 8A nz---- 2 TXA MOV A,X ;A=X 9A ------ 2 TXS MOV S,X ;S=X A9 nn nz---- 2 LDA #nn MOV A,nn ;A=nn A2 nn nz---- 2 LDX #nn MOV X,nn ;X=nn A0 nn nz---- 2 LDY #nn MOV Y,nn ;Y=nn |
A5 nn nz---- 3 LDA nn MOV A,[nn] ;A=[nn] B5 nn nz---- 4 LDA nn,X MOV A,[nn+X] ;A=[nn+X] AD nn nn nz---- 4 LDA nnnn MOV A,[nnnn] ;A=[nnnn] BD nn nn nz---- 4* LDA nnnn,X MOV A,[nnnn+X] ;A=[nnnn+X] B9 nn nn nz---- 4* LDA nnnn,Y MOV A,[nnnn+Y] ;A=[nnnn+Y] A1 nn nz---- 6 LDA (nn,X) MOV A,[[nn+X]] ;A=[WORD[nn+X]] B1 nn nz---- 5* LDA (nn),Y MOV A,[[nn]+Y] ;A=[WORD[nn]+Y] A6 nn nz---- 3 LDX nn MOV X,[nn] ;X=[nn] B6 nn nz---- 4 LDX nn,Y MOV X,[nn+Y] ;X=[nn+Y] AE nn nn nz---- 4 LDX nnnn MOV X,[nnnn] ;X=[nnnn] BE nn nn nz---- 4* LDX nnnn,Y MOV X,[nnnn+Y] ;X=[nnnn+Y] A4 nn nz---- 3 LDY nn MOV Y,[nn] ;Y=[nn] B4 nn nz---- 4 LDY nn,X MOV Y,[nn+X] ;Y=[nn+X] AC nn nn nz---- 4 LDY nnnn MOV Y,[nnnn] ;Y=[nnnn] BC nn nn nz---- 4* LDY nnnn,X MOV Y,[nnnn+X] ;Y=[nnnn+X] |
85 nn ------ 3 STA nn MOV [nn],A ;[nn]=A 95 nn ------ 4 STA nn,X MOV [nn+X],A ;[nn+X]=A 8D nn nn ------ 4 STA nnnn MOV [nnnn],A ;[nnnn]=A 9D nn nn ------ 5 STA nnnn,X MOV [nnnn+X],A ;[nnnn+X]=A 99 nn nn ------ 5 STA nnnn,Y MOV [nnnn+Y],A ;[nnnn+Y]=A 81 nn ------ 6 STA (nn,X) MOV [[nn+x]],A ;[WORD[nn+x]]=A 91 nn ------ 6 STA (nn),Y MOV [[nn]+y],A ;[WORD[nn]+y]=A 86 nn ------ 3 STX nn MOV [nn],X ;[nn]=X 96 nn ------ 4 STX nn,Y MOV [nn+Y],X ;[nn+Y]=X 8E nn nn ------ 4 STX nnnn MOV [nnnn],X ;[nnnn]=X 84 nn ------ 3 STY nn MOV [nn],Y ;[nn]=Y 94 nn ------ 4 STY nn,X MOV [nn+X],Y ;[nn+X]=Y 8C nn nn ------ 4 STY nnnn MOV [nnnn],Y ;[nnnn]=Y |
48 ------ 3 PHA PUSH A ;[S]=A, S=S-1 08 ------ 3 PHP PUSH P ;[S]=P, S=S-1 (flags) 68 nz---- 4 PLA POP A ;S=S+1, A=[S] 28 nzcidv 4 PLP POP P ;S=S+1, P=[S] (flags) |
CPU Arithmetic/Logical Operations |
69 nn nzc--v 2 ADC #nn ADC A,nn ;A=A+C+nn 65 nn nzc--v 3 ADC nn ADC A,[nn] ;A=A+C+[nn] 75 nn nzc--v 4 ADC nn,X ADC A,[nn+X] ;A=A+C+[nn+X] 6D nn nn nzc--v 4 ADC nnnn ADC A,[nnnn] ;A=A+C+[nnnn] 7D nn nn nzc--v 4* ADC nnnn,X ADC A,[nnnn+X] ;A=A+C+[nnnn+X] 79 nn nn nzc--v 4* ADC nnnn,Y ADC A,[nnnn+Y] ;A=A+C+[nnnn+Y] 61 nn nzc--v 6 ADC (nn,X) ADC A,[[nn+X]] ;A=A+C+[word[nn+X]] 71 nn nzc--v 5* ADC (nn),Y ADC A,[[nn]+Y] ;A=A+C+[word[nn]+Y] |
E9 nn nzc--v 2 SBC #nn SBC A,nn ;A=A+C-1-nn E5 nn nzc--v 3 SBC nn SBC A,[nn] ;A=A+C-1-[nn] F5 nn nzc--v 4 SBC nn,X SBC A,[nn+X] ;A=A+C-1-[nn+X] ED nn nn nzc--v 4 SBC nnnn SBC A,[nnnn] ;A=A+C-1-[nnnn] FD nn nn nzc--v 4* SBC nnnn,X SBC A,[nnnn+X] ;A=A+C-1-[nnnn+X] F9 nn nn nzc--v 4* SBC nnnn,Y SBC A,[nnnn+Y] ;A=A+C-1-[nnnn+Y] E1 nn nzc--v 6 SBC (nn,X) SBC A,[[nn+X]] ;A=A+C-1-[word[nn+X]] F1 nn nzc--v 5* SBC (nn),Y SBC A,[[nn]+Y] ;A=A+C-1-[word[nn]+Y] |
29 nn nz---- 2 AND #nn AND A,nn ;A=A AND nn 25 nn nz---- 3 AND nn AND A,[nn] ;A=A AND [nn] 35 nn nz---- 4 AND nn,X AND A,[nn+X] ;A=A AND [nn+X] 2D nn nn nz---- 4 AND nnnn AND A,[nnnn] ;A=A AND [nnnn] 3D nn nn nz---- 4* AND nnnn,X AND A,[nnnn+X] ;A=A AND [nnnn+X] 39 nn nn nz---- 4* AND nnnn,Y AND A,[nnnn+Y] ;A=A AND [nnnn+Y] 21 nn nz---- 6 AND (nn,X) AND A,[[nn+X]] ;A=A AND [word[nn+X]] 31 nn nz---- 5* AND (nn),Y AND A,[[nn]+Y] ;A=A AND [word[nn]+Y] |
49 nn nz---- 2 EOR #nn XOR A,nn ;A=A XOR nn 45 nn nz---- 3 EOR nn XOR A,[nn] ;A=A XOR [nn] 55 nn nz---- 4 EOR nn,X XOR A,[nn+X] ;A=A XOR [nn+X] 4D nn nn nz---- 4 EOR nnnn XOR A,[nnnn] ;A=A XOR [nnnn] 5D nn nn nz---- 4* EOR nnnn,X XOR A,[nnnn+X] ;A=A XOR [nnnn+X] 59 nn nn nz---- 4* EOR nnnn,Y XOR A,[nnnn+Y] ;A=A XOR [nnnn+Y] 41 nn nz---- 6 EOR (nn,X) XOR A,[[nn+X]] ;A=A XOR [word[nn+X]] 51 nn nz---- 5* EOR (nn),Y XOR A,[[nn]+Y] ;A=A XOR [word[nn]+Y] |
09 nn nz---- 2 ORA #nn OR A,nn ;A=A OR nn 05 nn nz---- 3 ORA nn OR A,[nn] ;A=A OR [nn] 15 nn nz---- 4 ORA nn,X OR A,[nn+X] ;A=A OR [nn+X] 0D nn nn nz---- 4 ORA nnnn OR A,[nnnn] ;A=A OR [nnnn] 1D nn nn nz---- 4* ORA nnnn,X OR A,[nnnn+X] ;A=A OR [nnnn+X] 19 nn nn nz---- 4* ORA nnnn,Y OR A,[nnnn+Y] ;A=A OR [nnnn+Y] 01 nn nz---- 6 ORA (nn,X) OR A,[[nn+X]] ;A=A OR [word[nn+X]] 11 nn nz---- 5* ORA (nn),Y OR A,[[nn]+Y] ;A=A OR [word[nn]+Y] |
C9 nn nzc--- 2 CMP #nn CMP A,nn ;A-nn C5 nn nzc--- 3 CMP nn CMP A,[nn] ;A-[nn] D5 nn nzc--- 4 CMP nn,X CMP A,[nn+X] ;A-[nn+X] CD nn nn nzc--- 4 CMP nnnn CMP A,[nnnn] ;A-[nnnn] DD nn nn nzc--- 4* CMP nnnn,X CMP A,[nnnn+X] ;A-[nnnn+X] D9 nn nn nzc--- 4* CMP nnnn,Y CMP A,[nnnn+Y] ;A-[nnnn+Y] C1 nn nzc--- 6 CMP (nn,X) CMP A,[[nn+X]] ;A-[word[nn+X]] D1 nn nzc--- 5* CMP (nn),Y CMP A,[[nn]+Y] ;A-[word[nn]+Y] E0 nn nzc--- 2 CPX #nn CMP X,nn ;X-nn E4 nn nzc--- 3 CPX nn CMP X,[nn] ;X-[nn] EC nn nn nzc--- 4 CPX nnnn CMP X,[nnnn] ;X-[nnnn] C0 nn nzc--- 2 CPY #nn CMP Y,nn ;Y-nn C4 nn nzc--- 3 CPY nn CMP Y,[nn] ;Y-[nn] CC nn nn nzc--- 4 CPY nnnn CMP Y,[nnnn] ;Y-[nnnn] |
24 nn xz---x 3 BIT nn TEST A,[nn] ;test and set flags 2C nn nn xz---x 4 BIT nnnn TEST A,[nnnn] ;test and set flags |
E6 nn nz---- 5 INC nn INC [nn] ;[nn]=[nn]+1 F6 nn nz---- 6 INC nn,X INC [nn+X] ;[nn+X]=[nn+X]+1 EE nn nn nz---- 6 INC nnnn INC [nnnn] ;[nnnn]=[nnnn]+1 FE nn nn nz---- 7 INC nnnn,X INC [nnnn+X] ;[nnnn+X]=[nnnn+X]+1 E8 nz---- 2 INX INC X ;X=X+1 C8 nz---- 2 INY INC Y ;Y=Y+1 |
C6 nn nz---- 5 DEC nn DEC [nn] ;[nn]=[nn]-1 D6 nn nz---- 6 DEC nn,X DEC [nn+X] ;[nn+X]=[nn+X]-1 CE nn nn nz---- 6 DEC nnnn DEC [nnnn] ;[nnnn]=[nnnn]-1 DE nn nn nz---- 7 DEC nnnn,X DEC [nnnn+X] ;[nnnn+X]=[nnnn+X]-1 CA nz---- 2 DEX DEC X ;X=X-1 88 nz---- 2 DEY DEC Y ;Y=Y-1 |
CPU Rotate and Shift Instructions |
0A nzc--- 2 ASL A SHL A ;SHL A 06 nn nzc--- 5 ASL nn SHL [nn] ;SHL [nn] 16 nn nzc--- 6 ASL nn,X SHL [nn+X] ;SHL [nn+X] 0E nn nn nzc--- 6 ASL nnnn SHL [nnnn] ;SHL [nnnn] 1E nn nn nzc--- 7 ASL nnnn,X SHL [nnnn+X] ;SHL [nnnn+X] |
4A 0zc--- 2 LSR A SHR A ;SHR A 46 nn 0zc--- 5 LSR nn SHR [nn] ;SHR [nn] 56 nn 0zc--- 6 LSR nn,X SHR [nn+X] ;SHR [nn+X] 4E nn nn 0zc--- 6 LSR nnnn SHR [nnnn] ;SHR [nnnn] 5E nn nn 0zc--- 7 LSR nnnn,X SHR [nnnn+X] ;SHR [nnnn+X] |
2A nzc--- 2 ROL A RCL A ;RCL A 26 nn nzc--- 5 ROL nn RCL [nn] ;RCL [nn] 36 nn nzc--- 6 ROL nn,X RCL [nn+X] ;RCL [nn+X] 2E nn nn nzc--- 6 ROL nnnn RCL [nnnn] ;RCL [nnnn] 3E nn nn nzc--- 7 ROL nnnn,X RCL [nnnn+X] ;RCL [nnnn+X] |
6A nzc--- 2 ROR A RCR A ;RCR A 66 nn nzc--- 5 ROR nn RCR [nn] ;RCR [nn] 76 nn nzc--- 6 ROR nn,X RCR [nn+X] ;RCR [nn+X] 6E nn nn nzc--- 6 ROR nnnn RCR [nnnn] ;RCR [nnnn] 7E nn nn nzc--- 7 ROR nnnn,X RCR [nnnn+X] ;RCR [nnnn+X] |
CPU Jump and Control Instructions |
4C nn nn ------ 3 JMP nnnn JMP nnnn ;PC=nnnn 6C nn nn ------ 5 JMP (nnnn) JMP [nnnn] ;PC=WORD[nnnn] 20 nn nn ------ 6 JSR nnnn CALL nnnn ;[S]=PC+2,PC=nnnn 40 nzcidv 6 RTI RETI ;(from BRK/IRQ/NMI) ;P=[S], PC=[S] 60 ------ 6 RTS RET ;(from CALL) ;PC=[S]+1 |
10 dd ------ 2** BPL nnn JNS nnn ;N=0 plus/positive 30 dd ------ 2** BMI nnn JS nnn ;N=1 minus/negative/signed 50 dd ------ 2** BVC nnn JNO nnn ;V=0 no overflow 70 dd ------ 2** BVS nnn JO nnn ;V=1 overflow 90 dd ------ 2** BCC/BLT nnn JNC/JB nnn ;C=0 less/below/no carry B0 dd ------ 2** BCS/BGE nnn JC/JAE nnn ;C=1 above/greater/equal/carry D0 dd ------ 2** BNE/BZC nnn JNZ/JNE nnn ;Z=0 not zero/not equal F0 dd ------ 2** BEQ/BZS nnn JZ/JE nnn ;Z=1 zero/equal |
00 ---1-- 7 BRK Force Break B=1,[S]=PC+1,[S]=P,I=1,PC=[FFFE] -- ---1-- 7 /IRQ Interrupt B=0,[S]=PC, [S]=P,I=1,PC=[FFFE] -- ---1-- 7 /NMI NMI B=0,[S]=PC, [S]=P,I=1,PC=[FFFA] -- ---1-- T+6? /RESET Reset B=1,S=S-3, I=1,PC=[FFFC] |
IRQs are executed whenever "/IRQ=LOW AND I=0". NMIs are executed whenever "/NMI changes from HIGH to LOW". |
18 --0--- 2 CLC CLC ;Clear carry flag C=0 58 ---0-- 2 CLI EI ;Clear interrupt disable bit I=0 D8 ----0- 2 CLD CLD ;Clear decimal mode D=0 B8 -----0 2 CLV CLV ;Clear overflow flag V=0 38 --1--- 2 SEC STC ;Set carry flag C=1 78 ---1-- 2 SEI DI ;Set interrupt disable bit I=1 F8 ----1- 2 SED STD ;Set decimal mode D=1 |
EA ------ 2 NOP NOP ;No operation |
CPU Illegal Opcodes |
87 nn ------ 3 SAX nn STA+STX [nn]=A AND X 97 nn ------ 4 SAX nn,Y STA+STX [nn+Y]=A AND X 8F nn nn ------ 4 SAX nnnn STA+STX [nnnn]=A AND X 83 nn ------ 6 SAX (nn,X) STA+STX [WORD[nn+X]]=A AND X A7 nn nz---- 3 LAX nn LDA+LDX A,X=[nn] B7 nn nz---- 4 LAX nn,Y LDA+LDX A,X=[nn+Y] AF nn nn nz---- 4 LAX nnnn LDA+LDX A,X=[nnnn] A3 nn nz---- 6 LAX (nn,X) LDA+LDX A,X=[WORD[nn+X]] B3 nn nz---- 5* LAX (nn),Y LDA+LDX A,X=[WORD[nn]+Y] |
00+yy nzc--- SLO op ASL+ORA op=op SHL 1 // A=A OR op 20+yy nzc--- RLA op ROL+AND op=op RCL 1 // A=A AND op 40+yy nzc--- SRE op LSR+EOR op=op SHR 1 // A=A XOR op 60+yy nzc--v RRA op ROR+ADC op=op RCR 1 // A=A+op+cy C0+yy nzc--- DCP op DEC+CMP op=op-1 // A-op E0+yy nzc--v ISC op INC+SBC op=op+1 // A=A-op-(1-cy) |
07+xx nn 5 nn [nn] 17+xx nn 6 nn,X [nn+X] 03+xx nn 8 (nn,X) [WORD[nn+X]] 13+xx nn 8 (nn),Y [WORD[nn]+Y] 0F+xx nn nn 6 nnnn [nnnn] 1F+xx nn nn 7 nnnn,X [nnnn+X] 1B+xx nn nn 7 nnnn,Y [nnnn+Y] |
0B nn nzc--- 2 ANC #nn AND+ASL A=A AND nn, C=N ;bit7 to carry 2B nn nzc--- 2 ANC #nn AND+ROL A=A AND nn, C=N ;same as above 4B nn nzc--- 2 ALR #nn AND+LSR A=(A AND nn) SHR 1 6B nn nzc--v 2 ARR #nn AND+ROR A=(A AND nn), V=Overflow(A+A), A=A/2+C*80h, C=A.Bit6 CB nn nzc--- 2 AXS #nn CMP+DEX X=(X AND A)-nn EB nn nzc--v 2 SBC #nn SBC+NOP A=A-nn cy? BB nn nn nz---- 4* LAS nnnn,Y LDA+TSX A,X,S = [nnnn+Y] AND S |
xx ------ 2 NOP (xx=1A,3A,5A,7A,DA,FA) xx nn ------ 2 NOP #nn (xx=80,82,89,C2,E2) xx nn ------ 3 NOP nn (xx=04,44,64) xx nn ------ 4 NOP nn,X (xx=14,34,54,74,D4,F4) xx nn nn ------ 4 NOP nnnn (xx=0C) xx nn nn ------ 4* NOP nnnn,X (xx=1C,3C,5C,7C,DC,FC) xx ------ - KIL (xx=02,12,22,32,42,52,62,72,92,B2,D2,F2) |
8B nn nz---- 2 XAA #nn ((2)) TXA+AND A=X AND nn AB nn nz---- 2 LAX #nn ((2)) LDA+TAX A,X=nn BF nn nn nz---- 4* LAX nnnn,X LDA+LDX A,X=[nnnn+X] 93 nn ------ 6 AHX (nn),Y ((1)) [WORD[nn]+Y] = A AND X AND H 9F nn nn ------ 5 AHX nnnn,Y ((1)) [nnnn+Y] = A AND X AND H 9C nn nn ------ 5 SHY nnnn,X ((1)) [nnnn+X] = Y AND H 9E nn nn ------ 5 SHX nnnn,Y ((1)) [nnnn+Y] = X AND H 9B nn nn ------ 5 TAS nnnn,Y ((1)) STA+TXS S=A AND X // [nnnn+Y]=S AND H |
AHX {adr} = stores A&X&H into {adr} SHX {adr} = stores X&H into {adr} SHY {adr} = stores Y&H into {adr} |
CPU Assembler Directives/Syntax |
65XX-style 80XX-style Expl. .native .nocash select native or nocash syntax *=$c100 org 0c100h sets the assumed origin in memory *=*+8 org $+8 increments origin, does NOT produce data label label: sets a label equal to the current address label=$dc00 label equ 0dc00h assigns a value or address to label .by $00 db 00h defines a (list of) byte(s) in memory .byt $00 defb 00h same as .by and db .wd $0000 dw 0000h defines a (list of) word(s) in memory .end end indicates end of source code file |nn [|nn] force 16bit "00NN" instead 8bit "NN" #<nnnn nnnn AND 0FFh isolate lower 8bits of 16bit value #>nnnn nnnn DIV 100h isolate upper 8bits of 16bit value N/A (?) fast label ensure relative jump without page crossing N/A (?) slow label ensure relative jump with page crossing |
.65xx Select 6502 Instruction Set .nes Create NES ROM-Image with .NES extension .c64_prg Create C64 file with .PRG extension/stub/fixed entry .c64_p00 Create C64 file with .P00 extension/stub/fixed entry/header .vic20_prg Create VIC20/C64 file with .PRG extension/stub/relocated entry end entry End of Source, the parameter specifies the entrypoint |
CPU Glitches |
CPU The 65XX Family |
6501 Some sort of 6502 prototype 6502 Used in the CBM floppies and some other 8 bit computers. 6507 Used in Atari 2600, 28pins (only 13 address lines, no /IRQ, no /NMI). 6510 Used in C64, with built-in 6bit I/O port. 7501 Used in C16,C116,Plus/4, with built-in 7bit I/O Port, without /NMI pin. 8500 Used in C64-II, with different pin-outs. 8501 Same as 7501 8502 Used in C128s. |
65C02 Extension of the 6502 65SC02 Small version of the 65C02 which lost a few opcodes again. 65CE02 Extension of the 65C02, used in the C65. 65816 Extended 6502 with new opcodes and 16 bit operation modes. 2A03 Nintendo NES/Famicom, modified 6502 with built-in sound controller. |
CPU Local Usage |
Hardware / Soldering |
Nocash SRAM Circuit |
- one-directional 4bit highspeed upload (when joystick is not moved) - bi-directional 1bit transmission for upload/download/debug terminal - works with external carts (if parallel cable disconnected or all high) - upload with automatic reset (autostart) - works with any older/newer one/two-directional PC parallel port - supports almost all existing cartridge types (except eight games) |
_____________ _____________ D0-7 --|D0-7 | D0-7 --|D0-7 | A0-6,8-10 --|A06,8-10 | A0-6,8-10 --|A0-6,8-10 | XA7,11 --|A7,11 | XA7,11-14 --|A7,11-14 | VCC --|A12-15 EPROM | /WRS --|/WE SRAM | /MREQ --|/CS 64Kx8 | /MREQ --|/CS 32Kx8 | /PROM.DTA3 --|/OE 27C512 | /SRAM.DTA2 --|/OE 62C256 | |_____________| |_____________| |
XA7 --------- A7 /RES.DTA4 ---|<|--- /RES,TP2,C27(+) XA11 --------- A11 /PROM.DTA3 --[10K]-- VCC R/W --------- /WRS /SRAM.DTA2 --[10K]-- VCC LPT.DTA0 --------- SWCHB.5,PIA.18 CART.DTA5 --[10K]-- VCC LPT.DTA1 --------- SWCHB.4,PIA.19 XA12 --[10K]-- VCC LPT.BUSY --------- SWCHB.2,PIA.22 XA13 --[10K]-- VCC LPT./STB --------- SWCHA.0,PIA.8 XA14 --[10K]-- VCC LPT./AUTOLF --------- SWCHA.2,PIA.10 ____ LPT./INIT --------- SWCHA.4,PIA.12 A12 --|AND \__ CS,SLOT.18 LPT./SELECT --------- SWCHA.6,PIA.14 CART.DTA5 --|____/ LPT.GND --------- GND A12 --|NAND\__ /MREQ CS,SLOT.18 --/cut/-- A12 PHI2 --|____/ |
____ _______ A11 --/cut/--- XA11 A6 --| |-------------|LE | GND ---------- 1K A7 --|NOR | D0 --|D0 Q0|-|<|- XA11 LPT.DTA6 ----- 3F A12 --| | D1 --|D1 Q1|-|<|- XA12 ____ R/W --| | D2 --|D2 Q2|-|<|- XA13 3F ___|INV \_____________| | D3 --|D3 Q3|-|<|- XA14 |____/ /3F |____| D4 --|D4 Q4|-- 1K A11 ---|NOR | ____ D5 --|D5 Q5|-- 4K 3F ---| |__|INV \--|<|--XA11 D6 --|D6 Q6|-- /16K 1K ---| | |____/ ____ D7 --|D7 Q7|-- /32K GND ---| | 3F --|AND \_______|/OE | GND ---|____| A11 --|____/ |_______| 74373 XA11 --[10K]-- VCC XA10 --[10K]-- VCC 1K --[10K]-- VCC |
____ ____ _________ PHI2 -| | A2 -----|NAND\_ ____ ____ 4K -|/CE1 /OE1|-- XRAM A5 ---| | /32K ---|____/ |XOR \_________| | 3F -|/CE2 /OE2|-- GND A6 ---|NAND| A1 -----|NAND\_|____/ /GOODA2 | |______|CLK RES|-- GND A7 ---| | 16K ----|____/ _______|NOR | | 74173 | A8 ---| | A2 -----|NAND\_ ____ GND | | A0 -|D0 Q0|-|<|-XA12 A9 ---| | 16K32K -|____/ |XOR \_________| | A1 -|D1 Q1|-|<|-XA13 A10 --| |_ A3 ------------|____/ /GOODA3 | | A2 -|D2 Q2|-|<|-XA14 A11 --|____| | GND --- XRAM ________________| | NC -|D3 Q3|-- NC ____ |______________| ____ /GOODFF | | |_________| /16K -|XOR \___ ___|INV \_________| | /16K --|XOR \__ 16K /32K -|____/ 16K32K A4 |____/ /GOODA4 |____| VCC --|____/ |
____ ____ A8 ---| |-- XRAM GND --/cut/-- XRAM XRAM -|OR \__ XA7 A9 ---|NOR | A7 --/cut/-- XA7 A7 --|____/ A10 ---| | R/W --/cut/-- /WRS ____ R/W --|OR \__ /WRS A11 ---| | /XRAM.DTA7 -----------------|AND \_______|____/ /XRAM.DTA7 ---|____| /3F -----------------|____/ WPROT |
__________ ____ A0..2 ---|D0-2 Q0-2|--- XA10..12 A10 --/cut/-- XA10 1K --|OR \-|<|-XA10 A12 -----|D3 Q3|--- NC GND --/cut/-- 1K A10 --|____/ A3 ------|WA0 RA0|--- A10 ____ 3F __|INV \-|<|- 1K A4 ------|WA1 RA1|--- A11 ____ _______/AND |--- A10 |____/ /GOODFF -|/WR /RD|________/OR | \____|--- A11 1K __|INV \_____ /1K |__________| 74170 \____|__/1K |____/ |
1 27C512 EPROM (or EEPROM, or FLASH, or other size, min 1KByte) 1 62C256 Static RAM (32KBytes or bigger) 1 74LS04 Hex Inverter 1 74LS08 Quad 2-input AND gate 1 74LS30 Single 8-input NAND gate 1 74LS32 Quad 2-input OR gate 1 74LS86 Quad 2-input XOR gate 1 74LS170 4x4 Register File open collector 1 74LS173 4-bit 3-state flip-flop with clock enable 2 74LS260 Dual 5-input NOR gate 1 74LS374 8-bit 3-state flip-flop 9 10K Ohm Resistors 11 1N4148 diodes (for /Reset signal, and ANDed "XAnn" and "1K" outputs) 1 Centronics socket 36pin female (and standard printer cable) |
0000 20 4A FC 9D FC 34 20 4C FC FF FC 26 20 25 FD 85 0010 85 20 25 FD 85 86 A9 00 85 80 A9 F0 85 81 20 87 0020 00 20 3F FC 4C 30 FC 20 87 00 20 3F FC 4C 30 FC 0030 20 4A FC D1 FC 2E 20 4C FC 25 FD 27 4C 87 00 A5 0040 82 20 FF FC A5 83 20 FF FC 60 A0 87 20 6C FC 85 0050 80 20 6C FC 85 81 20 6C FC 85 84 98 AA A0 00 B1 0060 80 95 00 C8 E8 C4 84 D0 F6 8A A8 60 BA F6 03 D0 0070 02 F6 04 A1 03 60 A0 00 84 80 20 AE 00 85 3F 20 0080 AE 00 85 81 0A F0 15 20 AE 00 91 80 18 65 82 85 0090 82 A9 00 65 83 85 83 C8 D0 ED F0 DE 60 20 BB 00 00A0 A6 85 DD 00 FF A0 00 B1 80 48 20 BB 00 68 18 65 00B0 82 85 82 A9 00 65 83 85 83 E6 80 D0 E3 E6 81 D0 00C0 DF A9 F0 85 81 A5 85 E6 85 C5 86 D0 D3 20 BB 00 00D0 60 20 B5 00 85 3F 20 B5 00 A2 58 86 49 8D 97 00 00E0 CD 00 FF A9 0F 85 3F A9 FF 8D 97 02 8D 80 02 8D 00F0 82 02 A9 00 85 81 8D 81 02 8D 83 02 6C FC FF 85 0100 84 A0 04 A9 10 06 84 69 03 8D 82 02 A9 10 2C 82 0110 02 D0 FB 06 84 69 03 8D 82 02 A9 10 2C 82 02 F0 0120 FB 88 D0 E1 60 A9 01 85 84 A9 10 2C 82 02 D0 FB 0130 0A 2D 82 02 C9 20 26 84 A9 10 2C 82 02 F0 FB 0A 0140 2D 82 02 C9 20 26 84 90 E0 A5 84 60 A9 10 2C 82 0150 02 D0 FB 0E 80 02 2C 82 02 F0 FB AD 80 02 60 A2 0160 00 BD 99 FD 20 FF FC E8 BD 99 FD D0 F4 A2 00 20 0170 25 FD DD AA FD D0 FE E8 E0 08 D0 F3 A9 2B 20 FF 0180 FC A2 00 A0 2B 20 4C FD DD AA FD F0 02 A0 2D E8 0190 E0 08 D0 F1 98 20 FF FC 60 4E 4F 24 32 4B 36 20 01A0 42 49 4F 53 20 56 31 2E 31 00 00 FF 55 AA 0F F0 01B0 3C C3 20 25 FD 85 3F 20 25 FD CD F7 FF 20 25 FD 01C0 85 3F 60 78 D8 A9 00 AA 95 00 9A E8 D0 FA A9 0E 01D0 85 3F A9 04 8D 83 02 A9 AA 8D 81 02 A2 28 86 49 01E0 20 5F FD 20 B2 FD 20 25 FD C9 31 F0 0B C9 34 F0 01F0 1A C9 44 F0 25 4C F5 FD A2 00 86 49 20 4A FC 76 0200 FC 27 20 4C FC 25 FD 27 4C 27 FC 20 4A FC 76 FC 0210 27 20 4C FC 4C FD 13 4C 27 FC 4C 00 FC FF FF FF 0220 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF .... FF FF FF ............................. FF FF FF 03F0 FF FF FF FF FF FF FF FF FF FF FF FF C3 FD 00 00 |
Composite Video and Audio Out |
LUM0'----[3K3]----o----------------o--------VIDEO OUT | | LUM1'----[2K2]----o 100p | | LUM2'----[1K]-----o TIA.COLOR---o-----[1K]-----GND | SYNC'----[330]----o TIA.AUDIO------------AUDIO OUT |
Type LUM0' LUM1' LUM2' SYNC' Atari 2600 4050.Pin2 4050.Pin12 4050.Pin15 4050.Pin4 Atari 2600A N/A N/A N/A N/A Atari Junior 4050.Pin2 4050.Pin10 4050.Pin15 4050.Pin12 |
Type COLOR AUDIO LUM0 LUM1 LUM2 SYNC PAL TIA.Pin9 TIA.Pin13 TIA.Pin7 TIA.Pin5 TIA.Pin6 TIA.Pin2 NTSC TIA.Pin9 TIA.Pin13+12 TIA.Pin8 TIA.Pin5 TIA.Pin7 TIA.Pin2 |
Using a PC Power Supply |
Chipset Pin-Outs |
25..28 D0..D7 4,2 VCC,GND 5..17 A0..A12 1,3,26 /RES,RDY,R/W 27,28 PHI0,PHI2 |
33..26 D0..D7 7..2,40 A0..A6 35 R/W 25 IRQ (NC) 36 /RS (A9) 37 /CS2 (A12) 38 CS1 (A7) 39 PHI2 34 /RES 8..15 PA0..PA7 (UDLR2, UDLR1) 1,20 GND,VCC 16..24 PB7..PB0 (DIF1,DIF0,NC,NC,COLOR,SELECT,RESET) |
20,23,22,1 VCC,VCC,GND,GND 14..19,33..34 D0..D7 32..27 A0..A5 21,24 /CS1 (A7), /CS2 (A12) 3,25,4,26,11 RDY,R/W,PHI0,PHI2,OSC 40..37,36,35 P0..P3 (POT0..3), T0..T1 (BUTTON1,2) 2,9,10 SYNC, COLOR, CADJ (+3.4V) |
7,5,6 LUM0,LUM1,LUM3 13,12,8 AUD,PALS,PALI ;AUD is audio AUD0+AUD1 merged on one pin |
8,5,7 LUM0,LUM1,LUM2 13,12,6 AUD0,AUD1,/BLK ;Pin6 exist in 2600 only (not 2600A?) |
3,5,7,9,11,14 INPUT A,B,C,D,E,F 2,4,6,10,12,15 OUTPUT A,B,C,D,E,F 1,8,13,16 VCC,GND,NC,NC |
Atari 2600 A=LUM0, B=SYNC, C=JOY2, D=JOY1, E=LUM1, F=LUM2 Atari 2600A N/A N/A N/A N/A N/A N/A Atari Junior A=LUM0, B=/RES, C=PALI, D=LUM1, E=SYNC, F=LUM2 |
Links |
http://www.atariage.com/system_items.html?SystemID=2600&ItemTypeID=ROM |
http://alienbill.com/vgames/guide/docs/stella.html |
http://oxyron.net/graham/opcodes.html |
http://nocash.emubase.de/2k6specs.txt http://nocash.emubase.de/2k6specs.htm |